My journey in constructing an 8 bit relay computer from scratch ... made from of a ton of solder, wires, lights, relays, sweat, tears, swearing and money.
ALU Design: Zero Detect
This post covers the design of the Zero Detect circuit which along with the 3-to-8 Function Decoder (covered in my last post) and the Condition Registers (next post) make up the ALU Control Card. The Zero Detect circuit ... wait for it ... detects when a value is zero. The value in question is taken from the data bus so in effect we're detecting when no bits are set. The output from this circuit is then passed to the Condition Registers so that the current value can be stored for future operations. The circuit itself is nice and simple:
If all inputs are off then the output Z is on otherwise, if any input is on, then Z is off. This design is taken from the Harry Porter Relay Computer as usual but this is one of the rarer cases where my translating the design to use DPDT relays doesn't increase the physical relay count:
To save space and wire links this design places the relays in alternating orientations so that the switches line up as required and all the inter-relay connections are made on the solder side of the board. With the relays and inputs/outputs hidden it looks like this:
... and that's it for the Zero Detect circuit. In the next post I'll cover the Condition Registers and then following that I'll move on to putting the ALU Control Card together.
This post covers the design of a 1-bit Arithmetic Unit that can add two input bits together (B and C) with carry in and out. Here's a schematic of the 1-bit Arithmetic Unit (based directly on the one used in the Harry Porter Relay Computer):
The diagram shows two 4PDT relays (just as before for the 1-bit Logic Unit) but this time the second relay has been rotated 180 degrees to make the diagram simpler to draw. B and C are the two 1-bit inputs that drive the relay coils, V is a permanent connection to the power supply and R is the resulting bit. CI is the carry in signal along with its inverted partner ~CI. Similarly CO is the carry output and ~CO is its inverted partner. It's the use of these regular and inverted carry signals that makes this design so neat ... and actually this isn't one of Harry's ... this design goes back a lot further.
This full adder circuit was actually invented by Konrad Zuse for his Z3 computer. The Z3 was also built out of relays just like t…
This post covers the design of the ALU Condition Registers which along with the 3-to-8 Function Decoder and Zero Detect circuit (both covered in my previous posts) make up the ALU Control Card. There are three Condition Registers in this computer: Carry: set when a bit is carried in the Arithmetic Unit (which can also indicate arithmetic overflow depending on the interpretation of the numbers being added).Zero: set when the ALU result is zero (all bits are off).Sign: set when the most significant bit is set (which would indicate a negative result for signed values). This condition has no direct meaning for unsigned numbers (other than indicating the number has a value of 128 or more).
When the ALU performs an operation the current values of these three conditions are stored in the condition registers so that they can be referred to in other operations. An example of this would be where given two numbers the first is negated and then added to the second ... if the two numbers are equal…
In the last post I introduced the design for the 1-bit Arithmetic Unit. This post covers connecting eight of these units together to make an 8-bit Arithmetic Unit along with result gating and increment functionality.
So, diving straight in, here is what eight of the 1-bit Arithmetic Units look like all together on the usual 55 x 40 hole pad board (excluding wire lines):
As before (with the Logic Unit card) things are a bit on the tight side but everything fits within the 40 hole horizontal confines of the pad board (as if by magic). Each of the 1-bit Arithmetic Units produces a 1-bit output and these need gating back on to the data bus so that the result doesn't conflict with any other Logic Unit output (or any future outputs from places like the Registers etc). With these additional relays added we get the following (this time including internal wire links in the 1-bit Arithmetic Units and result links between the Arithmetic Units and the gating relays):
This would now be enough…