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Showing posts from September, 2017

Control Design: Fetch and Increment

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The design of the computer's memory, incrementer and program counter are now complete but there's one last piece of the 'puzzle' required to get the computer running a program. The controller now needs updating to orchestrate the 'fetch and increment' cycle. This cycle retrieves the next instruction from memory (into the instruction register) and then increments the program counter to point at the next instruction in memory. In this post I'll cover the changes needed to the controller cards to implement this cycle.

The fetch/increment cycle consists of the following steps:
Select Program Counter on to Address Bus and whilst keeping selected:Read Memory on to Data Bus and whilst keeping read:Load Instruction RegisterLoad Increment Register (from incremented address bus value)Select Increment Register and whilst keeping selected:Load Program Counter Visualising these steps as a timing diagram we get the following:
As with the ALU, SETAB and MOV-8 instruction …

Memory Design (Part 2 of 2)

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In my last post I started the design for the computer's memory unit which is spread over two cards. With the lower memory card design in place its now time to finish the job and design the upper card which will interface the rest of the computer with the memory chip of the lower card.

Let's dive straight in by bringing up the board interconnects from the lower card:
The left two columns bring up the address bus for the memory chip which needs to be at 5V for a logic 1 and at ground for a logic 0. The third column brings up the outbound data bus which will sink 12V to ground for a logic 1 but holds at 12V for a logic 0 (effectively an inverse of what you'd expect). The fourth column brings up the inbound data bus which takes 5V for 1 and ground for 0 along with the write enable (WE) control line and output enable (OE) line which work in reverse (5V for disabled and ground for enabled). The last three connects to the right are power at 12V, ground for 5V and finally 5V. As y…

Memory Design (Part 1 of 2)

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In my last post I explained my decision to use a 'modern' memory chip in my relay computer ... I also alluded to there being some complexities in interfacing the rest of the computer with that memory chip. The memory unit will be spread over two cards and in this post I cover the design of the first half and expand on those 'complexities' a bit.

The memory chip I'm using is from the '62' family of CMOS 256Kbit (32K x 8) Static RAM ... effectively meaning it can store 32,768 separate 8 bit values referenced by a 15bit address bus. Buying chips can be a bit of a 'needle in a haystack' when you're buying through one of the larger electronics suppliers (I use Mouser). Knowing the chip number isn't enough to actually buy one and doing a search on Mouser for '62256 memory' narrows it down to 61 matches. I can narrow it down further as I know I need through-hole mounting (not surface mount) and that gets me to 6 matches. Next choice is acc…