Memory Design (Part 2 of 2)
Let's dive straight in by bringing up the board interconnects from the lower card:
First 'translation' job is to take the computer data bus, which is 12V for a logic 1 and disconnected for a 0, and wire that out to 5V for 1 and ground for 0. That's not overly complicated and looks like this:
Let's turn now to the data bus feed coming back from the memory chip which will also need gating so that it only influences the data bus of the computer when needed:
To get the memory value all the way out to the computer data bus there's a bit more translation required. In this case if the memory chip is putting out 5V on a line the relay driver will sink 12V to ground whereas if the memory chip is at ground on a line the relay driver will hold at 12V (logically inverted). To make this work this is the only place in the computer where we play with the 'other' side of the relay coil (which is usually soldered to ground):
The final part of the data bus 'picture' is to operate the write enable (WE) and output enable (OE) lines of the memory chip which as mentioned earlier operate in reverse of what you'd expect: 5V to disable and ground to enable. Only one additional relay is required:
That completes the data bus wiring but seems a shame not to fill the remaining space of the card with yet more relays so let's go for that:
So, that's ended up as one of the 'busier' card designs in the computer and it's one where I'll need to be careful with the wiring when constructing. Nonetheless that's the memory unit design complete and ready to go and as always you can find a PDF version on my Google drive here.
With the memory card, program counter and incrementer design in the bag we're very close to having a computer that can run a program in memory. In the next post I'll cover the final piece of the puzzle which is to update the controller card to orchestrate using these three units together.